1/6 data briefing september 2000 this is brief data from stmicroelectronics. details are subject to change without notice. for complete data, please contact your nearest sales office or smartcard products divison, rousset, france. fax: (+33) 4 42 25 87 29 ST22XJ64 smartcard 32-bit risc mcu with 64 kbytes eeprom and javacard ? hardware execution ST22XJ64 features n 32-bit risc cpu with 24-bit linear memory addressing n 96 kbytes user rom n 4 kbytes user ram n 64 kbytes user eeprom 32-bit risc cpu n dual instruction set, javacard ? and native n 4-stage pipeline n 16 general purpose 32-bit registers, and 10 special registers n 4 maskable interrupt levels n supervisor and user modes security n cpu security instructions C clear all general purpose registers instruction C hardware des and 3des instructions C fast multiply and accumulate instructions for public key cryptography n cpu dpa/spa countermeasures n fips-140 random number generator n eeprom flash programming mode n clock and power management n voltage, clock frequency and temperature sensors memory n highly reliable cmos eeprom 0.35 m technology C error correction code for single bit fail within a 32-bit word C 10 year data retention, 100,000 erase/write cycles endurance C 1 to 128 bytes erase or program in 2 ms typical n high performance memory C dual memory busses for data and instruction C byte, short (2) and word (4) load and store C address auto increment for vector walking n advanced memory protection C memory protection unit for application firewalling and peripheral access control n three working stacks C java stack with both 16 and 32-bit accesses C user and supervisor mode stacks other features n hardware asynchronous serial interface (uart) C contact assignment compatible iso 7816-2 C serial io ports compatible iso 7816-3 n 3 20-bit timers with interrupt, internal or external clock n central interrupt controller with up to 16 input lines n 33 mhz internal clock n external clock from 1 mhz to 5 mhz n 3 v 10% or 5 v 10% supply voltage n power consumption 6 ma @ 5 mhz n temperature range -25 c to +85 c n power reduction in standby mode n esd protection greater than 5000 v
2/6 ST22XJ64 description the ST22XJ64, is a member of the smartj ? plat- form using a 32-bit reduced instruction set com- puter (risc) core to execute both native risc instructions and javacard 2.1 technology instruc- tion (bytecodes) directly. see figure 1, smartj? platform architecture n direct javacard bytecode execution provides high performance advantage over processors that emulate the javacard bytecode instruction set. n the ST22XJ64 features a 24-bit wide linear addressing capability and includes 96 kbytes of user rom, 4 kbytes of user ram and 64 kbytes of user eeprom. memory and peripheral accesses are controlled by a memory protection unit that allows to implement firewalls between applications. volatile memory and non-volatile memory are accessed via two different busses, allowing simultaneous accesses to code and data. memory load and stores can be performed at byte, short (2-bytes), or word (4-bytes) granularity, with optional pointer auto increment. n the st22 core includes dedicated des instructions for secret key cryptography, and a fast multiply and accumulate instruction for public key cryptography (rsa). the st22 core also includes specific instructions for security, such as clear all general purpose registers in a single cycle. n the ST22XJ64 has clock and power management, 2 configurable timers, a central interrupt controller and a fips-140 random number generator. n the ST22XJ64 has two execution modes. java mode is used when javacard 2.1 bytecodes are being executed. native mode is used for long javacard 2.1 bytecodes, native methods and system routines. the processor enters java mode when a dispatch instruction is encountered. when executing in native mode, there are two privilege levels, user and system. some instructions can only be executed in system mode. the cpu core has 16 32-bit general purpose registers, as well as 10 special registers of variable length. instructions are of variable length, from 1 to 4 bytes in native mode. figure 1. smartj ? platform architecture rom eeprom ram peripherals ram bus rom bus timer asi .... power mngt. clock mngt. iso 7816 security m p u rng .... .... scp 160b/prz 32-bit risc core
ST22XJ64 3/6 n special instructions exist for single-cycle stack operations, a frequent occurrence in java code. short branches and conditional branches within a 1 kbyte block or the entire 16 mbyte instruction space are supported. ST22XJ64 has four stages of pipeline in native mode: fetch, decode, execute and write-back. in java mode, there are five stages of pipeline: bytecode-fetch, bytecode-decode, decode, execute and write-back. n the chip also features a very high performance asynchronous serial interface to support high speed serial communication protocols compatible with both contact and contactless iso standards. n it is manufactured using the highly reliable st cmos eeprom 0.35 m m technology. embedded software n the hardware software interface (hsi) is a set of c interfaces to the ST22XJ64 eeprom memory and peripherals. the drivers are: C eeprom C asynchronous serial input C central interrupt controller C timer C random number generator C clock manager C memory protection unit C security controller C interrupt / abort handlers important note: the hsi driver software layer is the only way to have access to the ST22XJ64 peripherals and eeprom memory. software development environment modularity, flexibility and methodology are the key words for the smartj development tools platform. using the same interface, the developers are able to create, compile and debug a project. the smartj integrated development environment (ide) includes: n a code generation chain with capability for using c, c++ compilers, an assembler/linker and a java compiler. n an instruction set simulator, a cycle accurate simulator, c, c++, and java source level debuggers and hardware emulation tools. oem development license types the ST22XJ64 is a product based on the smartj platform. developers have two types of licenses for access to the technology: n stlda the smartj technology license and distribution agreement for standard oem developers (embedded operating system and application software developers) and card embedders. they must use the smartj hardware software interface (hsi) metalayer communication interface to access the ST22XJ64 hardware resources. the validation of the embedded software will be done using the simulators of the code validation tools chain. n sptla the smartj platform technology license agreement for oem platform developers. the sptla is for developers who need to develop a customised architecture using the platform blocks assembled with a proprietary custom hardware plug-in logic block and associated firmware. the complete code validation tools chain including the vhdl emulator, must be used for both the hardware, software development integration and validation. the complete code validation tool chain is accessible to oem platform developers licensees only.
4/6 ST22XJ64 figure 2. smartj ? platform concept 1. smartj platform technology license agreement required 2. smartj technology license and distribution agreement required smartj platform st22 core plus rom ram eeprom size definition std peripherals & security asi, timers, security mechanisms,... customs plugs-in (1) smartj ide smartj-tools pack-cd smartj h/w development vhdl library (1) smartj iso 15408 certified embedded library hsi (2) memory & std peripherals drivers crypto (2) certified crypto library (des, 3des, rsa, sha,...) scp 160a/prz
ST22XJ64 5/6 figure 3. smartj ? ide
6/6 ST22XJ64 figure 4. smartj ? code generation tools figure 5. smartj ? code validation tools 1. smartj platform technology license agreement required 3. contact st sales office java compiler c/c++ standard libraries c/c++ compiler linker/class loader/optimizer c/c++ source java source asm source native assembler object files java byte code java class libraries scp 160c/prz debugger gui debugger core > console.exe third party tools st player peripherals models integrated development environment smartcard pod smart card reader cycle accurate simulator instruction set simulator ice drivers jtag controller s mart j smartcard vhdl emulator fpga board (1) scp 160d/prz
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